Dead time control in a switching circuit

ABSTRACT

A dc-to-dc converter has two field effect transistors ( 35, 36 ) connected in series between an input terminal ( 37 ) and a ground terminal ( 38 ). Adjustment of the dead time when both transistors ( 35, 36 ) are off is carried out by providing Kelvin feedback connections ( 71, 72, 67, 68 ) directly across the drain ( 39, 44 ) and source ( 43, 40 ) of one or both of the transistors ( 35, 36 ), so bypassing signal line resistance and inductances.

The invention relates to a switching circuit, and a method of operatinga switching circuit, particularly but not exclusively to a dc-to-dcvoltage converter circuit.

Direct current (dc) to dc converters are well known in the art, and areused to convert from one dc voltage to another, for example to provide a1.5V voltage rail from a 12V voltage supply.

One type of converter, a synchronous dc-dc converter, operates byalternately switching a first terminal of an inductor coil between aninput voltage, for example, 12V, and ground. An output is taken at asecond terminal of the inductor coil, buffered by an output capacitor.The switches used in such a device may be driven by a pulse widthmodulated (PWM) signal, the duty cycle (the ratio of the length of timethat the signal is high compared to that when it is low) of whichdetermines the magnitude of the output signal.

A known type of synchronous dc-dc converter is illustrated schematicallyin FIG. 1. The switches which control the current flowing in theinductor coil 1 are, in this example, field effect transistors (FETs). Afirst FET 2, generally referred to as the control FET, or high-sidetransistor, connects a first terminal 3 of the inductor 1 to a dc inputvoltage supplied at a supply terminal 4. A second FET 5, generallyreferred to as the synchronous FET (sync FET) or low-side transistor,connects the first terminal 3 of the inductor 1 to a ground terminal 6.The first terminal 3 of the inductor 1 is generally referred to as theswitch node.

The signal at the switch node 3 feeds through the inductor 1 and acrossa capacitor 7, to an output terminal 8.

The control FET 2 and sync FET 5 are driven by respective drivers 9, 10.A control circuit 11 has an input terminal 12 fed by a pulse widthmodulation (PWM) signal and another input fed from the output terminal8, via a feedback path 13. The control circuit 11 supplies alternatingcontrol signals 14, 15 to control the control and sync FETs 2, 5 tomaintain a desired voltage at the output 8 by switching the FETs 2, 5off and on alternately. The duty cycle of the PWM signal input atterminal 12 is modulated to achieve the desired voltage on the output 8.

Examples of such dc-dc converters include those presented in WO98/49607to Intel Corporation and U.S. Pat. No. 5,479,089 to Lee.

One feature of synchronous dc-dc converters is that the control and syncFETs 2, 5 should not be on simultaneously. Even when the FETs 2, 5 areonly momentarily on at the same time, large currents will flow betweenthe supply and ground terminals 4, 6. This phenomenon is known ascross-conduction. Accordingly, the control circuit 11 is arranged toensure that only one of the two FETs 2, 5 is on at any one time. This isachieved by introducing a dead time during which both of the FETs 2, 5are off, usually by delaying turn on of each FET until the other isdetermined to be off.

One way of implementing the control circuit 11 is to monitor twovoltages. The voltage at the switch node 3 is monitored to prevent theswitching on of the sync FET 5 until the control FET 2 is switched off,while the voltage at the gate of the sync. FET 5 is monitored to preventthe control FET 2 switching on until the sync FET 5 is switched off.WO98/49607 describes a circuit of this type, as does U.S. Pat. No.5,479,089.

The dead time, when neither the control FET 2 nor the sync FET 5 isconducting, depends on the transistor threshold voltage and thecapacitance of the sync FET 5, which vary widely due to themanufacturing spread of parameters of the chosen FET, as well asaccording to the individual choice of FET. The dead time is alsodependent on the propagation delay through the monitoring circuit andthe delay time of FET driver circuits. The resulting dead time maytherefore be larger than the dead time required to simply preventcross-conduction.

During the dead time, the inductor current flows through the body diode16 of the sync FET 5. This causes body diode losses to occur. At the endof the dead time period, particularly when the opposite switch isactivated, large diode reverse recovery losses, switching losses andelectromagnetic induction (EMI) occur. Minimising the dead time istherefore beneficial in reducing body diode losses. If the dead time ismade small enough such that the body diode does not conduct, powerefficiency is improved through a reduction in switching losses, reverserecovery losses and EMI.

WO 02/063752 describes a method of minimising the dead time of a dc-dcconverter by monitoring a voltage at the switch node and comparing thiswith a predetermined voltage.

When either the control FET or sync FET switches off, both FETs willthen be off for the duration of the dead time. The inductor continues todraw current through the body diode of the sync FET and the voltageacross the body diode reaches about 0.8V.

However, although such a circuit reliably avoids cross-conduction, thereremains an appreciable dead time, when neither FET is switched on, of atleast the delay time of the driver plus the turn-on time of the chosenFET. This dead time is about 30 ns using current technology.

An alternative approach is described in U.S. Pat. No. 6,396,250. In thisapproach, controllable delays are provided on the inputs to the gates ofthe transistors, controlled by a feedback loop signal taken from theswitch node. Although this approach delivers benefits over WO 02/063752,it continues to have certain drawbacks. One of these is that it assumesthe current in the coil to be always in the direction of the load at themoment the control FET is switched off. While this may be true understeady state conditions, it may not be true under transient conditions.

The principles of the analogue implementation of U.S. Pat. No. 6,396,250are shown in FIG. 2. Feedback is taken from the switch node 3 todetermine a delay to be added to the control FET control signal on line14. This is achieved by sampling the voltage between the switch node 3and the ground terminal 6 using sampling circuitry 20. This comprisesfirst and second switches 21, 22, which apply the switch node voltage,across respective sampling capacitors 23, 24, to an error amplifier 25.A voltage source 26 is used to ensure that the dead time is notminimised to the extent that cross-conduction occurs. The output of theerror amplifier 25 is fed into a voltage controlled delay (VCD) circuit27, which introduces a variable delay to the PWM control signal 14. Theresulting signal 28 is used to drive the control FET 2, and causes adelay before it switches on, or dead time. A similar arrangement (notshown) of sampling and VCD circuits is used to drive the sync FET 5.

During and after the dead time period, there is a large variance betweenthe voltage at the source 29 of the sync FET 5 and the ground rail 6.This is caused by a self-inductance 30 (shown in dotted outline) ofabout 1 nH between the source 29 of the sync FET 5 and the ground rail6. At the start of the dead time period, when the sync FET 5 is switchedoff, current flows through the sync FET body diode 16. At the end of thedead time period, when the control FET 2 is switched on, the currentflowing through the body diode 16 starts to decrease. This changingcurrent causes a potential difference across the self-inductance 30, andthe voltage difference observed between the switch node 3 and the groundrail 6 is accordingly not as large in magnitude as the drain-sourcevoltage between the source 29 and the drain 31 of the sync FET 5. Due tothis, circuits that measure the voltage between the switch node 3 andground rail 6 would inaccurately detect the time at which the sync FETbody diode 16 stops conducting. Reducing or even eliminating the periodduring which the switch node 3 to ground rail 6 voltage is a certainmagnitude, as suggested in U.S. Pat. No. 6,396,250, results in a circuitin which body diode conduction occurs, and hence losses in the circuitwill remain. 25 In some switching circuits, such as those with a smallor negligible load, current may flow backwards through the inductor,i.e. from the second terminal 17 of the inductor 1 towards the firstterminal 3, when both the control and sync FETs 2, 5 are switched off.The switch node voltage thus increases, and current flows through thebody diode 32 of the control FET 2. This causes the voltage at thesource 33 of the control FET 2 to become a forward diode voltage higherthan the voltage at its drain 34. Measuring the voltage across the drain31 and source 29 of the sync FET 5 does not give an indication of thedead time in this case. Energy loss in the control FET body diode 32 isnot as significant as that in the sync FET body diode 16. However, incertain circuits, dead time minimisation is still beneficial. Forinstance, in switching circuits used for applications such as digitalaudio amplification, too much dead time may cause signal distortion. Itis therefore beneficial for a switching circuit to be able to reducedead time in circumstances in which the inductor current is reversed.

The present invention aims to address the above problems.

According to a first aspect of the invention there is provided aswitching circuit having a first field effect transistor and a secondfield effect transistor connected in series between an input terminaland a ground terminal, wherein a source of the first transistor isconnected to the drain of the second transistor and a source of thesecond transistor is connected to the ground terminal, the circuitcomprising control means for driving said first and second transistorsalternately such that there is a dead time period during which bothtransistors are off and means for adjusting the length of the dead timeperiod according to a voltage difference between the drain and thesource of the first or second transistor.

By adjusting the dead time period in accordance with the voltage acrossthe drain and the source of the second transistor, as opposed to betweendrain and ground, the effect of the self-inductance of the source toground connection is eliminated and a more accurate measurement of thevoltage across the body diode of the second transistor is possible. Thiscan permit the transistors to be controlled more effectively so that thedead time, and hence loss, can be minimised.

Adjusting the dead time period in accordance with the voltage across thedrain and source of the first transistor, also referred to as thecontrol FET, enables the dead time to be reduced in the case when theinductor current flows towards the switch node. This is because aforward diode voltage difference occurs across the body diode of thecontrol FET and is measurable across the drain and source of the controlFET, rather than across the drain and source of the sync FET.

The first and/or second transistors may be constructed on an integratedcircuit die, each of said transistors having respective source and drainregions on the die. The switching circuit may further comprise sensingmeans for sensing the voltage difference between the drain and source ofthe first or second transistors, wherein the sensing means has a firstconnection which is directly connected to the source region of the firstor second transistor.

By providing a source connection on the die, the inductance between thesource region and the ground terminal can be bypassed.

The sensing means can also have a second connection which is directlyconnected to the drain region of the first or second transistor.

By making the source and drain connections across the die, theconnections can comprise Kelvin connections, in which the signalfeedback lines are separated from the current path, so eliminatingerrors associated with the resistance and inductance of the signallines.

According to the invention, there is also provided a method of operatinga switching circuit having a first field effect transistor and a secondfield effect transistor connected in series between an input terminaland a ground terminal, wherein a source of the first transistor isconnected to the drain of the second transistor and a source of thesecond transistor is connected to the ground terminal, the methodcomprising driving the first and second transistors alternately suchthat there is a dead time period during which both transistors are off;and adjusting the length of the dead time period according to a voltagedifference between the drain and the source of the first or secondtransistor.

A further drawback to the approach of U.S. Pat. No. 6,396,250 is thatthe sampling circuitry in the analogue circuit arrangement haslimitations. Referring again to FIG. 2, this circuitry relies onaccurately driving the first and second switches 21, 22. The firstswitch 21 enables the sampling circuitry 20 to sample the switch node 3voltage during the conduction of the sync FET 5, while the second switch22 enables the sampling circuitry 20 to sample the switch node 3 duringthe dead time period. The sampled signals are then compared at the erroramplifier 25, to provide a voltage to the voltage controlled delaycircuit 27. In practice, errors in the driving of the switches 21, 22and sampling circuits would further impair the dead time minimisation.

The digital approach described in U.S. Pat. No. 6,396,250 also hascertain drawbacks in the design of its sampling circuitry. In thedigital approach, the dead time delay is incremented or decrementedaccording to whether or not the voltage at the switch node reaches acertain threshold voltage. Accordingly, the dead time is not directlyreduced in proportion to either the magnitude of the body diode voltageor the length of time for which this voltage occurs. Both of theseparameters influence body-diode conduction loss. In cases where thevalue of these parameters is high, reducing the dead time more quicklytherefore minimises loss in the circuit.

Furthermore, the size of the decrement of dead time loss will have abearing on the amount of minimisation which is achievable.

The present invention further aims to address the above-describedproblems.

According to a second aspect of the present invention, there is provideda switching circuit having a first field effect transistor and a secondfield effect transistor connected in series between an input terminaland a ground terminal, wherein a source of the first transistor isconnected to the drain of the second transistor and a source of thesecond transistor is connected to the ground terminal, the circuitcomprising control means for driving said first and second transistorsalternately such that there is a dead time period during which bothtransistors are off, and means for adjusting the length of the dead timeperiod according to a voltage difference between the drain of the secondtransistor and the ground terminal, wherein the adjusting means adjuststhe length of the dead time period according to the length of time forwhich the voltage difference exceeds a threshold value.

The adjusting means may adjust the length of the dead time periodaccording to the magnitude by which the voltage difference exceeds thethreshold voltage.

The adjusting means may also adjust the length of the dead time periodsuch that the length of the dead time period is exponentially dependenton the magnitude by which the voltage difference exceeds the thresholdvoltage, and/or linearly dependent on the length of time for which thevoltage difference exceeds the threshold value.

For a better understanding of the invention, embodiments thereof willnow be described, purely by way of example, with reference to theaccompanying drawings, in which:

FIG. 1 illustrates a prior art synchronous dc-dc converter;

FIG. 2 illustrates a prior art synchronous dc-dc converter with addeddead time according to the switch-node voltage with respect to ground;

FIG. 3 is a simplified schematic of a synchronous dc-dc converteraccording to the invention;

FIG. 4 schematically illustrates an integrated circuit implementation ofa dc-dc converter according to the invention;

FIG. 5 schematically illustrates a further example of a synchronousdc-dc converter according to invention;

FIG. 6 is a graph showing representations of the PWIM control signal andswitch node voltage signal in the synchronous dc-dc converters shown inFIGS. 3 and 5;

FIG. 7 schematically illustrates the sensing and adaptive dead timereduction circuits of the converter of FIG. 5; and

FIGS. 8 a, 8 b and 8 c are graphs showing voltage signals at monitoredpoints in a synchronous dc-dc converter according to the invention.

Referring to FIG. 3, as in conventional synchronous dc-dc convertercircuits, a control FET 35 and sync FET 36 are arranged in seriesbetween an input terminal 37 and a ground terminal 38. In this examplethese are field effect transistors, however, other types of switchingdevice can be used. The drain 39 of the control FET 35 is connected tothe input terminal 37, and the source 40 of the sync FET 36 is connectedto the ground terminal 38. A first terminal 41 of an inductor 42, theterminal generally referred to as the switch node, is connected to thesource 43 of the control FET 35 and the drain 44 of the sync FET 36.Although an inductor 42 is used in this example, a transformer with twoor more isolated coils may also be used. The signal at the switch node41 feeds through the inductor 42 and across a capacitor 45 to an outputterminal 46.

An output from a pulse width modulation (PWM) control circuit (notshown) is applied to a control input terminal 48. The PWM controlcircuit alters the duty cycle of a PWM signal according to feedback fromthe output terminal 46 of the converter. The PWM control circuit is notshown in the drawings since suitable PWM generation schemes are wellknown to the skilled person. In other embodiments of the inventionalternative control signals may be used, such as pulse frequencymodulation (PFM). The control signal 48 is split to form control and async control signals 50, 51 which are supplied to sensing and adaptivedead time reduction (ADR) circuits 52, 53. The sensing and ADR circuits52, 53 each take feedback from the drain 44 and source 40 of the syncFET 36 via feedback lines 54 and 55, and use this to alter delay times Dand E, which are introduced to the control and sync FET control signals50, 51 respectively to produce signals with minimised dead time delay onfirst and second control lines 56, 57. These signals 56, 57 are appliedat the gates of the control and sync FETs 35, 36 via appropriate drivercircuitry 58, 59, to maintain a desired voltage at the output 46 byswitching the FETs 35, 36 off and on alternately.

Taking feedback directly from the drain 44 and source 40 of the sync FET36, enables the sensing and ADR circuits 52, 53 to accurately detect thevoltage across the body-diode 60 of the sync FET 36, and to control theFETs 35, 36, so that the dead time, and hence loss, is minimised.

Although two sensing and ADR circuits 52, 53 are illustrated, onecircuit could be arranged to supply the control signals for both thecontrol and sync FETs 35, 36. Having individual circuits for eachenables the delay time before the sync FET gate goes high to bedifferent to the delay time before the control FET gate goes high, whichallows more flexibility in dead time minimisation.

The dc-dc converter of FIG. 3, in one example, is implemented in anintegrated circuit, as shown in FIG. 4. This illustrates how the controlFET 35 and sync FET 36, as well as the driver, sensing and ADR circuitry(shown as 65) may be arranged in an integrated circuit. The controlcircuit input/output pins 66 are provided for input and outputconnections relating to the driver, sensing and ADR circuitry 65. Inputand output pins 37, 41 and 38, in this example, are the input voltageterminal 37, switch node 41 and ground terminal 38 respectively.

Referring to FIG. 4, the feedback lines 67, 68 are connected directly tothe sync FET drain 44 and source 40 regions of the integrated circuitdie, and hence bypass the inductance between the source 40 and theground terminal 38. Furthermore, the current path signal lines 69, 70are completely separate from the feedback lines 67, 68, so making theconnections to the source 40 and drain 44 regions Kelvin connections.This has the effect of eliminating the error caused when the feedbackconnections 67, 68 are taken across even a small portion of the signallines 69, 70, which have a resistance and an inductance, and thereforeinfluence the voltage measured, particularly whilst the sync FET 36 isconducting.

Similar Kelvin connection lines 71, 72 may be connected to the controlFET drain 39 and source 43 regions of the integrated circuit die. Theseconnections are necessary for the case in which the inductor current ofthe converter flows towards the switch node 41, thus requiring thevoltage across the source 43 and drain 39 of the control FET 35 to bemonitored.

Alternative implementations of the invention are possible. For example,the invention may be implemented in a multi-chip module (MCM), with orwithout the use of Kelvin connections. Also, discrete FET packages withsmall series self-inductances, such as DirectFET as manufactured byInternational Rectifier, or LFPAK manufactured by Philips Semiconductorsmay be used as the control and sync FETs. However, even the smallinductances of these packages would cause error to the feedbackmeasurement in circuits that exhibit large current changes over smalltime intervals.

FET packages having multiple source connections may also be used,whereby one of these connections would be reserved for the sync andcontrol FET source feedback connections. Examples of such FET packagesare the power SO8 and LFPAK packages manufactured by PhilipsSemiconductors.

The control FET may be implemented using a PMOS transistor, which can bean advantage in integrated circuit implementations.

FIG. 5 schematically illustrates a further example of a synchronousdc-dc converter according to the invention. In this example, signals arefed back from five monitoring points in the circuit, the gate 79, drain44 and source 40 of the sync FET 36, and the gate 80 and source 43 ofthe control FET 35. The signals at the drain 44 and source 40 of thesync FET 36 are fed back via lines 54, 55 to control and sync sensingcircuits 81, 82, one for each of the control FET 35 and sync FET 36driving circuitry. The control and sync sensing circuits 81, 82 in thisexample determine when the drain-source voltage of the sync FET 36reaches a threshold value, and then output a signal exponentiallydependent on the drain-source voltage above this threshold. The outputsfrom the control and sync sensing circuits 81, 82 are applied to controland sync adaptive dead time reduction (ADR) circuits 83 and 84respectively.

The control ADR circuit 83 also receives a PWM signal, and the sync ADRcircuit 84 receives an inverse PWM signal (inverted by inverter 85),both of which originate from a control circuit whose output is connectedto a PWM control input terminal 48. The control circuit alters the dutycycle of the PWM signal according to feedback from the output terminal46 of the converter. The generator is not shown in the drawings sincesuitable generation schemes are well known to the skilled person. Inother embodiments of the invention alternative control signals may beused, such as pulse frequency modulation (PFM).

The control and sync ADRs 83, 84 introduce delays D, E, which aredependent on the input from the sensing circuits 81, 82, to the PWMsignal. The resulting signals are then applied to drive the control andsync FETs 35, 36. This causes a delay to the turning on of each of thecontrol and sync FETs 35, 36, thus introducing a dead time when both thecontrol FET 35 and sync FET 36 are off. Having individual sensing andADR circuits 81 to 84 for the control FET 35 and sync FET 36 asillustrated, enables them to have independent dead time delays, althoughone sensing and one ADR circuit could be configured to provide a delayto the turning on of both FETs.

Each of the driving signals from the ADR circuits passes through a firstand a second logic OR gates 87, 88 before being applied to the controland sync FETs 35, 36. The first and second OR gates 87, 88 areincorporated so that neither the control nor the sync FET 35, 36 turnson until the driving signal at the gate of the other has fallen below athreshold voltage Vth1, Vth2, i.e. the FET has turned off, or the outputfrom the respective ADR circuit 83, 84 has gone high. A controlcomparator 89 determines whether the gate-source voltage of the controlFET 35 has fallen below a certain threshold voltage Vth1 supplied byvoltage source 95. The control comparator 89 compares the voltage at thegate 80 of the control FET 35, applied at its first input, to the sum ofthe source voltage of the control FET 35 and the threshold voltage Vth1,applied at its second input. The output from this comparator 89 is thenfed into a first input of second OR gate 88, and the output from thesync ADR circuit 84 is fed into its second input. Sync comparator 90determines whether the gate-source voltage of the sync FET 36 has fallenbelow a threshold voltage Vth2 supplied by voltage source 96. The synccomparator 90 compares the voltage at the gate 79 of the sync FET 36,applied at its first input, to the sum of the source voltage of the syncFET 36 and the threshold voltage Vth2, applied at its second input. Theoutput from the sync comparator 90 is then fed into a first input of thefirst OR gate 87, and the output from the control ADR circuit 83 is fedinto the second input.

Additionally, control and sync logic AND gates 91, 92 are incorporatedin series between the output of the control and sync OR gates 87, 88 andthe control and sync FETs 35, 36 respectively. The control AND gate 91has one input taken from the output of the control OR gate 87 and theother from PWM signal. This is incorporated so that the control FET 35is off when the PWM signal is low. The sync AND gate 92 has one inputtaken from the output of OR gate 88 and the other from the inverse ofPWM signal. This is incorporated so that the sync FET 36 is off when theinverse of the PWM control signal is low.

In alternative embodiments of the invention other combinations of logiccircuitry may be used. For instance, the OR gates 87, 88 with theirrespective comparators 89, 90, and/or the AND gates 91, 92 may beomitted entirely, or omitted from one of the sync FET 36 or control FET35 logic circuitry.

Control and sync buffer amplifiers 93, 94 are also added in series toreceive the control signals with added dead time, and to output gatedriving signals to drive the control and sync FETs 35, 36.

In further embodiments, alternative control and sync sensing circuitsare provided which are similar to control and sync sensing circuits 81,82, but which take feedback signals from the drain 39 and source 43 ofthe control FET 35, in the case in which current flows from the secondterminal of the inductor towards the first during the dead time period.These alternative sensing circuits could be provided either in additionto or in place of control and sync sensing circuits 81 and 82. In eithercase the control and sync ADR circuits 83, 84 would be configured toreceive signals from the alternative control and sync sensing circuits.

The operation of the embodiment of FIG. 5 will now be described in moredetail with reference to FIG. 6 of the accompanying drawings.

The sequence of PWM switching pulses 100 input at the PWM input terminal48 is shown in the upper part of FIG. 6. The voltage 101 on the sync FETdrain 44 is illustrated in the lower part of FIG. 6.

When the PWM signal 100 falls at a first time 102, the control FET 35 isswitched off due to the low value at the PWM input to the control ANDgate 91. This causes the voltage at the sync FET drain 44 to start tofall, as current continues to be drawn by the inductor 42, but ratherthan passing through the control FET 35 or the sync FET 36 which areboth off, the current passes through the body diode 60 of the sync FET36. This process ends with the voltage on the sync FET drain 44 beingdetermined by the voltage drop across the body diode 60 of the sync FET36, i.e. around −0.8V (during second time period 103).

When the voltage across the sync FET drain 44 and source 40 falls belowa predetermined reference value, for example −0.4V, the sync sensingcircuit 82 is triggered. The output from this circuit is a current whichis supplied to the sync ADR circuit 84 and which determines a delay,‘E’. This current, in this embodiment, is exponentially dependent (up toa certain maximum value) on the amount of the sensed voltage differenceacross the drain 44 and source 40 of the sync FET 36 which is greaterthan the predetermined reference voltage, and active during the timethat the sensed voltage difference is greater than the referencevoltage. Accordingly, the delay ‘E’, and therefore the dead time, isexponentially dependent on the magnitude by which the voltage differenceexceeds the threshold voltage and linearly dependent on the length oftime for which the voltage difference exceeds the threshold value.

When the control signal 100 falls at the first time 102, the sync ADR 84thus introduces delay ‘E’ (second time period 103) to the controlsignal, so that time E will lapse, unless the output of comparator 89has gone high, before the sync FET 36 is driven high. In normal circuitoperation, the detection of the sync FET drain-source voltage(body-diode voltage) and the application of the detected signal to theADR circuitry 83, 84 is likely to take longer than the dead time delayrequired. For this reason, the delays D and E will generally bedependent only upon previously detected body-diode voltages.

When the control FET gate 80 falls below Vth1, the output of the controlcomparator 89 will immediately go high. If the delay E introduced by thesync ADR 84 is longer than the propagation delay through the controlcomparator 89 from the time when the control FET gate 80 fell belowthreshold voltage Vth1, the output of OR gate 88 will already have gonehigh before delay E has lapsed and thus the sync ADR 84 output has noeffect. This may occur during the first few initialising cycles of theconverter circuit. The output from the sync OR gate 88 is fed into thesync logic AND gate 92, which only allows the sync FET 36 to be drivenhigh if the sync OR gate 88 output is high, and if the inverted PWMsignal is high. As the PWM signal is low, this is the case, and the syncFET 36 is turned on.

With the sync FET 36 switched on, and entering the linear region, thevoltage on the sync FET drain 44 rises during a third time period 104 toapproximately −0.1V.

When the control signal 100 rises at a fourth time 105, first the syncFET 36 is switched off due to the low signal at the inverse PWM input ofthe sync AND gate 92. Again, current is transferred to the body diode 60of the sync FET 36, which makes the drain-source voltage of the sync FET36 more negative, as shown at a fifth time period 106. When the voltagefalls below a predetermined voltage, for example −0.4V, the controlsensing circuit 81 is triggered. The output from this circuit is acurrent which is supplied to the sync ADR circuit 83 and whichdetermines a delay, ‘D’. This current, in this embodiment, isexponentially dependent (up to a certain maximum value) on the amount ofthe sensed voltage difference across the drain 44 and source 40 of thesync FET 36 which is greater than the predetermined reference voltage,and active during the time that the sensed voltage difference is greaterthan the reference voltage. Accordingly, the delay ‘D’, and thereforethe dead time, is exponentially dependent on the magnitude by which thevoltage difference exceeds the threshold voltage and linearly dependenton the length of time for which the voltage difference exceeds thethreshold value.

When the control signal 100 rises at the fourth time 15, the control ADR83 thus introduces delay ‘D’ (fifth time period 106) to the controlsignal, so that time D will lapse, unless the output of comparator 90has gone high, before the control FET 35 is driven high.

When the sync FET gate 79 falls below Vth2, the output of the synccomparator 90 will immediately go high. If the delay D introduced by ADR83 is longer than the propagation delay through the sync comparator 90from the time when the sync FET gate 79 fell below threshold voltageVth2, the output of the control OR gate 87 will already have gone highbefore delay D has lapsed and thus the control ADR 83 output has noeffect. This may occur during the first few initialising cycles of theconverter circuit. The output from the control OR gate 87 is fed intothe control logic AND gate 91, which only allows the control FET 35 tobe driven high if the control OR gate 87 output is high and the PWMsignal is high. As the PWM signal is high the control FET 35 is turnedon.

FIG. 7 illustrates the control sensing circuit 81 and control ADRcircuit 83 for driving the control FET 35. Referring firstly to thesensing circuit 81, two signals are inputted at first and second inputterminals 109 and 110. The source 40 and drain 44 of the sync FET 36 areconnected to these terminals 109 and 110 respectively (not shown). Theseterminals are connected to the cathodes of first and second diodes 111,112. The anode of the first diode 111 is connected to the emitterterminal of a first bipolar junction transistor (BJT) 113, the collectorand base terminals of which are both connected to a first current source114. First and second resistors 115, 116 are connected in series betweenthe base of the first BJT 113 and the anode of the first diode 111. Thebase terminal of a second BJT 117 is connected to a node connected inseries between the first and second resistors 115, 116, and the emitterterminal is connected to the anode of the second diode 112. The outputof sensing circuit 81 is taken at the collector of the second BJT 117,via a first FET 118 and into a current mirror circuit 119 in the controlADR circuit 83.

During the dead time period, the voltage at the drain 44 of the sync FET36 will, when the dead time is not minimised, become approximately 0.8Vmore negative than the voltage at the source 40. The first and secondresistors 115, 116 are arranged in this example such that when the syncFET 36 drain-source voltage reaches half of its peak voltage (−0.4V),this will increase the potential across the base-emitter junction of thesecond BJT 117 enough to allow conduction in the second BJT 117 currentpath. This current will increase exponentially (up to a certain maximum)as the sync FET drain-source voltage increases above half its peakvoltage.

The PWM signal 100 is inputted to the control ADR circuit 83 at a thirdinput terminal 120, passes through a one-shot circuit 121, and is usedto control the first FET 118 and a second FET 122. When the PWM signal100 becomes high, i.e. when the control FET 35 is to be turned on, thefirst FET 118 turns on and a current 11 flows through a first path ofthe current mirror circuit 119. In one circuit configuration, thiscurrent will increase by a factor of ten for every 120 mV that the bodydiode voltage is greater than at half its peak value. The second path ofthe current mirror 119 also then conducts a current 12. This path isconnected to the positive terminal of a comparator 123, as well as to afirst capacitor 124 and third resistor 125 which are in parallel betweenthe current mirror 119 and a ground terminal 126. The current 12 in thesecond current mirror path charges the first capacitor 124 and thevoltage at the positive input of the comparator 123 thus increases.

The negative input to the comparator 123 is connected to a supplyvoltage terminal 127, via a second capacitor 128, and to a groundterminal 129 via a series combination of the current path of the secondFET 122 and a second current source 130. The negative input to thecomparator 123 and the drain of the second FET 122 are also connected tothe source of a third FET 131, whose drain is connected to the supplyvoltage terminal 127 and whose gate is connected to the one-shot 121output.

The one-shot circuitry 121 is arranged such that its output rises tologic high when a rising PWM edge is detected, and falls to a logic lowsignal when a falling PWM edge is detected, or after a certain delay.Whilst the one-shot output is high, the second FET 122 conducts, and thethird FET 131 is off. The voltage at the negative input of thecomparator 123 thus falls from the supply voltage to ground over aperiod of time dependent on the value of the second capacitor 128 andthe magnitude of the current produced by the current source 130.

At the time when the falling voltage at the negative input of thecomparator thus reaches a level equal to the voltage at the positivecomparator 123 input, the output of the comparator 123 goes high, and adriving signal is outputted, via the output terminal 132, to turn on thecontrol FET 35.

When the PWM control signal goes low, or after a certain delay, firstand second FETs 118 and 122 are turned off and third FET 131 is turnedon. Accordingly, the first capacitor 124 starts to discharge through thethird resistor 125 causing the voltage at the positive input terminal ofthe comparator 123 to decrease very slightly. Also, the negative inputterminal of the comparator 123 is raised to the supply voltage by thethird FET 131, and the second capacitor 128 therefore discharges. Theoutput of the comparator 123 goes low, until the next positive PWMsignal 100 triggers the ADR circuitry 83. The voltage across the secondcapacitor 124, the value of the third resistor 125, and the rate of thefalling voltage at the negative comparator 123 input will determine thedelay to be added to the control FET control signal the next time thePWM signal 100 goes high.

The sensing and ADR circuits 82, 84 for driving the sync FET 36 areidentical to those for driving the control FET 35, but are configured tobe activated by an inverse PWM control signal. One way this could beachieved is by using the inverter 85 shown in FIG. 5, or equally byaltering the one-shot circuit 121. The third resistor 125 may bereplaced by a current source which is switched on for a fixed amount oftime during each period of the PWM signal 100. This means that the rateof discharge of the second capacitor 124 is independent of its voltagelevel and that the action of the ADR circuit becomes independent to theswitching frequency of the PWM signal 100.

In the case in which alternative control and sync sensing circuits areprovided which take feedback from the drain and source of the controlFET, rather than the sync FET, these would comprise pnp transistorsrather than the npn transistors illustrated in FIG. 7. If thealternative control and sync sensing circuits are provided in additionto control and sync sensing circuits 81, 82, the output from thealternative control and sync sensing circuits would be combined with theoutput 12 of the current mirror 119 of control and sync ADR circuits 83,84 respectively.

The first and second diodes 111, 112 are incorporated in the sensingcircuitry 81, 82 for protection of the base-emitter junction oftransistor 117 when the switch node 41 goes high. In alternativeembodiments, active (MOS) switches could be used in place of the passive(bipolar) diodes 111, 112 which automatically switch off when thedrain-source voltage of the sync FET 36 rises above a certain level.Also, in place of the vertical bipolar junction transistors 113, 117,lateral bipolar junction transistors could be used which can resist muchhigher reverse voltages, and accordingly the use of diodes 111, 112 maybe unnecessary. However, lateral bipolar junction transistors usuallyhave relatively small current amplification.

When using active (MOS) switches rather than diodes 111, 112, or whenusing lateral bipolar junction transistors in place of the verticalbipolar junction transistors 113, 117, and no diodes 111, 112, all ofthe voltage difference between drain 44 and source 40 of the sync FET 36would be applied across the base and emitter of transistor 117 ratherthan divided between the diodes 111, 112 and the base-emitter junction.Accordingly, the current I1 in the first current path of the currentmirror 119 would increase by a factor of 10 for every 60 mV that thevoltage difference across the drain 44 and source 40 of the sync FET 36is greater than a predetermined value, such as half of its maximumvalue.

Rather than using a single BJT 117, a Darlington configuration or afield effect transistor may be used, with diodes 111, 112 if necessary.The voltage across the first resistor 115 should be approximately equalto the predetermined reference voltage, which is, in the exampleillustrated in FIG. 7, equal to half the forward body diode voltage ofthe sync FET. The voltage across the first resistor 115 would preferablyhave the same temperature dependence as the forward body diode voltageof the sync FET.

When using field effect transistors in the place of BJT 117, the currentamplification will tend to be more quadratic than exponential inrelation to the voltage difference across the drain 44 and source 40 ofthe sync FET 36, unless used in the subthreshold or weak inversionregion where the amplification is exponential for very low currentdensities.

FIGS. 8 a to 8 c illustrate voltage levels of a dc-dc converter circuitaccording to the invention, with a load across the output of 10A. Eachof the graphs show the voltage levels during the fifth time period 106(see FIG. 6) when the PWM signal 100 goes high at time 105, the sync FET36 is turned off, and a delay ‘D’ is added by the control ADR circuitry83 before the control FET 35 is turned on. Curve A is the voltage at thesync FET source 40 with respect to ground 38. Curve B is the voltage atthe sync FET drain 44 with respect to ground 38, and Curve C is thedrain-source voltage of the sync FET 36.

FIG. 8 a illustrates the voltages at a time when dead time minimisationhas not yet occurred. It can be seen that there is a large variancebetween the sync FET source 40 (curve A) and the ground 38 when the deadtime minimisation occurs. This is caused by self-inductance of thesource 40 to ground 38 connection, and results in the voltage at thesync FET drain 44 with respect to ground 38 (curve B) not having aslarge a magnitude as the sync FET drain-source voltage (curve C). Thismeans that monitoring curve B to reduce dead time, as performed in theprior art, does not reduce body diode conduction, and therefore loss, tothe same extent as monitoring curve C. It can be seen that the bodydiode 60 conducts for a period 106 a of roughly 15 nanoseconds(illustrated by curve C).

FIG. 8 b illustrates the voltages after a further 4 microseconds, whendead time minimisation is almost finished. The body diode 60 nowconducts for substantially less time than at the start of theminimisation. Curve C suggests this time period 106 b to beapproximately half that at the start, i.e. 7.5 nanoseconds.

FIG. 8 c illustrates the voltages after a further 12 microseconds. Atthis stage dead time minimisation has finished, and, in this embodiment,the dead time has been reduced to a dead time 106 c of approximately 3.5nanoseconds. The voltage across the body diode (curve c) falls toapproximately −550 mV. Were prior art circuits which monitor the syncFET drain to ground voltage (curve B) to reduce their monitored voltageso that it is negative for only 3.5 nanoseconds, or drops to a minimumof −550 mV, the true dead time and body diode voltages (curve C) wouldbe much greater than those possible with the current invention.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications 30 may involve equivalent and other features which arealready known in the design, manufacture and use of synchronous dc-dcconverters and which may be used instead of or in addition to featuresalready described herein.

Although claims have been formulated in this application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel features orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention. The applicants hereby give notice that new claims maybe formulated to such features and/or combinations of such featuresduring the prosecution of the present application or of any furtherapplications derived therefrom.

For example, the embodiments described use the approach of the inventionfor controlling both transistors, but it is possible to use the approachonly for controlling one transistor, and not the other.

There is no need for both the transistors to be n-channel. For exampleeither the control FET or both the control and sync FETs could bep-channel. In this case, the control driving circuitry would need to beadjusted accordingly.

Further, although the described embodiments relate to a switchingvoltage converter the invention is also applicable to a switchingamplifier or any other switching power circuit having synchronousswitches.

1. A switching circuit having a first field effect transistor and asecond field effect transistor connected in series between an inputterminal and a ground terminal, wherein a source (of the firsttransistor is connected to the drain (4of the second transistor and asource of the second transistor is connected to the ground terminals,the circuit comprising: control means or driving the first and secondtransistors alternately such that there is a dead time period duringwhich both transistors are off; and means for adjusting the length ofthe dead time period according to a voltage difference between the drainand the source of the first or second transistor.
 2. A switching circuitaccording to claim 1, wherein the first and/or the second transistorsare constructed on an integrated circuit die, each of said transistorshaving respective drain and source regions on said die, furthercomprising sensing means for sensing the voltaglage difference betw18enthe drain and the source of the first or second transistors, whereinthis sensing means has a first connection, which is directly connectedto the source region of the first or second transistor.
 3. A switchingcircuit according to claim 2, wherein the sensing means has a secondconnection which is directly connected to the drain region of the firstor second transistor.
 4. A switching circuit according to claim 2,wherein the first and/or second connections are Kelvin connections.
 5. Aswitching circuit according to claim 2, wherein the sensing means sensesthe voltage difference during the dead time period.
 6. A switchingcircuit according to claim 1, wherein the adjusting means adjusts thelength of future dead time periods according to the voltage differenceduring the dead time period.
 7. A switching circuit according to claim1, wherein the adjusting means adjusts the length of the dead timeperiod according to the length of time that the voltage differenceexceeds a threshold voltage.
 8. A switching circuit according to claim1, wherein the adjusting means adjusts the length of the dead timeperiod according to the magnitude by which the voltage differenceexceeds a threshold voltage.
 9. A switching circuit according to claim1, wherein the adjusting means adjusts the length of the dead timeperiod such that the length of the dead time period is exponentiallydependent on the magnitude by which threshold voltage difference exceedsthe threshold voltage.
 10. A switching circuit according to claim 1,wherein the adjusting means adjusts the length of the dead time periodsuch that the length of the dead time period is linearly dependent onthe length of time for which the voltage difference exceeds a thresholdvalue.
 11. A switching circuit according to claim 1, comprisingcircuitry to prevent the first transistor from turning on until thesecond transistor has turned off.
 12. A switching circuit according toclaim 1, comprising circuitry to prevent the second transistor fromturning on until the first transistor has turned off.
 13. A dc-dcconverter circuit comprising the switching circuit of claim
 1. 14. Amethod of operating a switching circuit having a first field effecttransistor sand a second field effect transistor connected in seriesbetween an input terminal and a ground terminal, wherein a source of thefirst transistor (is connected to the drain of the second transistor anda source of the second transistor is connected to the ground terminal,the method comprising: driving the first and second transistorsalternately such that there is a dead time period during which bothtransistors are off; and adjusting the length of the dead time periodaccording to a voltage difference between the drain and the source ofthe first or second transistor.
 15. A switching circuit having a firstfield effect transistor and a second field effect transistor connectedin series between an input terminal and a ground terminal, wherein asource of the first transistor is connected to the drain of the secondtransistor and a source of the second transistor is connected to theground terminal, the circuit comprising: control means for driving saidfirst and second transistors alternately such that there is a dead timeperiod during which both transistors are off; and means for adjustingthe length of the dead time period according to a voltage differencebetween the drain of the second transistor and the ground terminal,wherein the adjusting means adjusts the length of the dead time periodaccording to the length of time for which the voltage difference exceedsa threshold value.
 16. A switching circuit according to claim 15,wherein the adjusting means adjusts length of the dead time periodaccording to the magnitude by which the voltage difference exceeds thethreshold voltage.
 17. A switching circuit according to claim 15,wherein the adjusting means adjusts the length of the dead time periodsuch that the length of the dead time period is exponentially dependenton the magnitude by which the voltage difference exceeds the thresholdvoltage.
 18. A switching circuit according to claim 15, wherein theadjusting means adjusts the length of the dead time period such that thelength of the dead time period is linearly dependent on the length oftime for which the voltage difference exceeds the threshold value.